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Silicon Labs /SiM3_NRND /SIM3L167_C /SPI_1 /CLKRATE

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Interpret as CLKRATE

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31282724232019161512118743000000000000000000000000000000000000000000CLKDIV

Description

Module Clock Rate Control

Fields

CLKDIV

Clock Divider.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data